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CD4089BMS
December 1992
CMOS Binary Rate Multiplier
conjunction with an up/down counter and control logic used to perform arithmetic operations (adds, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigometric functions, A/D and D/A conversions, and frequency division. For words of more than 4 bits, CD4089BMS devices may be cascaded in two different modes: an Add mode and a Multiply mode (see Figures 3 and 4). In the Add mode some of the gaps left by the more significant unit at the count of 15 are filled in by the less significant units. For example, when two units are cascaded in the Add mode and programmed to 11 and 13, respectively, the more significant unit will have 11 output pulses for every 16 input pulses and the other unit will have 13 output pulses for every 256 input pulses for a total of
11 16 + 13 189 = 256 256
Features
* High Voltage Type (20V Rating) * Cascadable in Multiples of 4 Bits * Set to "15" Input and "15" Detect Output * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Standardized Symmetrical Output Characteristics * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
In the Multiply mode the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second multiplier. Thus the output rate will be
11 16 x 13 16 = 143 256
Applications
* Numerical Control * Instrumentation * Digital Filtering * Frequency Synthesis
The CD4089BMS has an internal synchronous 4 bit counter which, together with one of the four binary input bits, produces pulse trains as shown in Figure 6. If more than one binary input bit is high, the resulting pulse train is a combination of the separate pulse trains as shown in Figure 6. The CD4089BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H2R H6P
Description
CD4089BMS is a low power 4 bit digital rate multiplier that provides an output pulse rate that is the clock-input-pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, there will be 13 output pulses for every 16 input pulses. This device may be used in
Pinout
CD4089BMS TOP VIEW
Functional Diagram
CLOCK 9 "15" OUT 1 C2 D3 16 VDD 15 B 14 A 13 CLEAR 12 CASCADE 11 INHIBIT IN (CARRY) 10 STROBE 9 CLOCK VDD = 16 VSS = 8 INHIBIT (CARRY) IN 11 SET TO "15" 4 CLEAR 13 7 1 4 BIT BINARY COUNTER BINARY RATE SELECT INPUTS ABCD 14 15 2 3 RATE SELECT LOGIC 10 STROBE CASCADE 12 6 5 OUT OUT
SET TO "15" 4 OUT 5 OUT 6 INHIBIT OUT (CARRY) 7 VSS 8
RATE OUTPUTS "15" OUT
INHIBIT (CARRY) OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3329
7-1064
Specifications CD4089BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+125oC -55oC +25o C
+125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC
+25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
1.5 4 -
V V V V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1065
Specifications CD4089BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN 1.2 .89 MAX 300 405 760 1026 180 243 200 270 UNITS ns ns ns ns ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock to Output Propagation Delay Clear to Out Propagation Delay Cascade to Out Transition Time
SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TTHL TTLH FCL
CONDITIONS (NOTES 1, 2) VDD = 5V, VIN = VDD or GND
Maximum Clock Input Frequency NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55 C, +25 C +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL5 VOL10 VOH5 VOH10 IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25 C, +125 C, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55 Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2
oC o o o o o o o o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 -
MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA
+125oC -55oC +125oC -55
oC oC
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
-55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125
oC
-55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC
7-1066
Specifications CD4089BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage Low Input Voltage High Propagation Delay Clock to Out SYMBOL VIL VIH TPHL4 TPLH4 CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 5V VDD = 10V VDD = 15V Propagation Delay Clock to Out Propagation Delay Clock to Inhibit Out TPHL1 TPLH1 TPHL5 VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Propagation Delay Clock to Inhibit Out TPLH5 VDD = 5V VDD = 10V VDD = 15V Propagation Delay Clear to Out Propagation Delay Cascade to Out Propagation Delay Clock to "9" or "15" Out TPHL2 TPLH2 TPHL3 TPLH3 TPHL6 TPLH6 VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Propagation Delay Inhibit In to Inhibit Out TPHL7 TPLH7 VDD = 5V VDD = 10V VDD = 15V Propagation Delay Set to Out TPHL8 TPLH8 VDD = 5V VDD = 10V VDD = 15V Transition Time TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TSU VDD = 5V VDD = 10V VDD = 15V Minimum Inhibit-In Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Maximum Clock Rise and Fall Time TRCL TFCL VDD = 5V VDD = 10V VDD = 15V NOTES 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 TEMPERATURE +25 C, +125 C, -55oC +25oC, +125oC, -55oC +25oC +25oC +25 C +25 C +25oC +25 C +25oC +25 C +25oC +25oC +25 C +25oC +25 C +25oC +25 C +25oC +25oC +25oC +25 C +25
oC o o o o o o o o o o
MIN +7 2.5 3.5 -
MAX 3 220 110 90 150 120 720 320 220 500 200 150 350 260 90 70 600 250 180 320 150 110 660 300 220 100 80 100 40 20 240 130 110 330 170 100 15 15 15
UNITS V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns s s s
+25oC +25
oC
+25oC +25
oC
+25oC +25 +25
oC oC
Maximum Clock Input Frequency Minimum Inhibit-In Setup Time
+25oC +25
oC
+25oC +25
oC
+25oC +25oC +25oC +25 +25
oC oC
+25oC +25
oC
+25oC +25
oC
7-1067
Specifications CD4089BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Set Removal Time SYMBOL TREM CONDITIONS VDD = 5V VDD = 10V VDD = 15V Minimum Clear Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Set or Clear Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25 C +25 C +25oC +25oC +25 C +25oC
o o o
NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2
TEMPERATURE +25 C +25oC +25 C +25oC +25 C +25
oC o o o
MIN -
MAX 150 80 50 60 40 30 160 90 60 7.5
UNITS ns ns ns ns ns ns ns ns ns pF
+25oC +25oC +25oC +25
oC
CIN
Any Input
MIN -2.8 0.2 VOH > VDD/2 -
MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit
UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) MIL-STD-883 METHOD 100% 5004 GROUP A SUBGROUPS 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A
7-1068
Specifications CD4089BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic BurnIn (Note 1) Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 1, 5-7 1, 5-7 1, 5-7 GROUND 2-4, 8-15 8 2, 4, 8, 10, 12-15 8 VDD 16 2-4, 9-16 3, 16 2-4, 9-16 1, 5-7 9 11 9V -0.5V 50kHz 25kHz
7-1069
CD4089BMS Logic Diagram
A
*14
B
*15
C
*2
STROBE D Qd Qc Qb Qa Qc Qb Qa Qb Qa Qa Qb Qc Qd
*10 *12
CASCADE OUT 6
*3
CLOCK
*9
CLEAR SYNCHRONOUS 4 BIT BINARY COUNTER
Qa Qa Qb Qb Qc Qc Qd Qd
OUT 5
*13
SET TO "15"
*4
INHIBIT IN
Qa
"15" 1
*11
INHIBIT OUT 7
Qa Qb Qc Qd VDD
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK VSS
FIGURE 1. LOGIC DIAGRAM
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1070
CD4089BMS
TRUTH TABLE INPUTS NUMBER OF PULSES OR INPUT LOGIC LEVEL (0 = Low; 1 = High; X = Don't Care) D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X 1 0 X C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X X X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X CLK 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 INH IN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 STR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 CAS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CLR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 X SET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OUTPUTS NUMBER OF PULSES OR OUTPUT LOGIC LEVEL (L = Low; H = High) OUT L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ** L H 16 L L OUT H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ** H * 16 H H INH OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L "15" OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ** 1 1 L L H
* Output same as the first 16 lines of this truth table (depending on values A, B, C, D) ** Depends on internal state of counter
MOST SIGNIFICANT DIGIT 1 1 0 1 A B C D CLOCK CASC INH IN ST CLEAR "15" INH OUT DRM 1 OUT OUT 1 0 1 1
LEAST SIGNIFICANT DIGIT A B C D CLOCK CASC INH IN ST CLEAR "15" INH OUT DRM 2 OUT OUT 1 1 0 1
MOST SIGNIFICANT DIGIT A B C D CLOCK CASC INH IN ST CLEAR "15" INH OUT DRM 1 OUT OUT 1 0 1 1
LEAST SIGNIFICANT DIGIT A B C D CLOCK CASC INH IN ST CLEAR "15" INH OUT DRM 2 OUT OUT
S
S
S
S
CLOCK
CLOCK
FIGURE 2. TWO CD4089BMS's CASCADED IN THE "ADD" MODE WITH A PRESET NUMBER OF 189 11 13 189 + = 16 256 256
FIGURE 3. TWO CD4089BMS's CASCADED IN THE "MULTIPLY" MODE WITH A PRESET NUMBER OF 143 11 13 143 + = 16 16 256
7-1071
CD4089BMS
CLOCK COUNTER STATE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
*
(LSB) INPUT A = H
INPUT B = H
INPUT C = H
OUTPUT WAVE TRAINS (TERM 6)
(MSB) INPUT D = H
*
AN OUTPUT BIT MAY BE FILLED IN THIS COUNTER STATE BY A LESS SIGNIFICANT CD4089 CASCADED IN THE ADD MODE
FIGURE 4. TIMING DIAGRAM
Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 8. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
7-1072
CD4089BMS Typical Performance Characteristics
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 200 AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
150 SUPPLY VOLTAGE (VDD) = 15V 10V 100
200 SUPPLY VOLTAGE (VDD) = 5V
150
5V 50
100 10V 50 15V
0
20
40 60 80 LOAD CAPACITANCE (CL) (pF)
100
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYP. PROPAGATION DELAY TIMES AS FUNCTION OF LOAD CAPACITANCE (CLOCK OR STROBE TO OUT)
105 8 POWER DISSIPATION PER (PD) (W)
6 4 2
FIGURE 10. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V
104 8
6 4 2
10V 10V 5V
103
8 6 4 2
102
8 6 4 2
CL = 50pF CL = 15pF
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
10 1 103 10 102 INPUT FREQUENCY (fIN) (kHz) 104
FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION: BOND PADS:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1073

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